1. 芯片设计工程师-安全
工作地： 美国
招聘人数： 1
· Responsibilities:
– RTL Design and implementation of MACSEC/IPSEC/AES/SHA/RSA cores for high performance networking application
– Create block-level micro-architecture specification and that outline interfaces, timing behavior, design tradeoffs, and performance goals
– Review vendor IP integration guidelines and verify the compliance throughout the design flow
– Run integrity check tools such as Lint/CDC/DFT/LEC/UPF to satisfy coding and implementation guidelines
– Participate in design verification process by reviewing test plans, coverage reports, writing assertions and other design modifications to improve verification quality
– Participate in physical implementation process by providing synthesis constraints, timing exceptions and making design updates to meet area, power and performance goals
– Be able to work and communicate with multi-site teams
– Responsible for the review of netlist releases (pre/post-route/eco, block/chip)
· Experience/Skills:
– Extensive experience with AES encryption, digital signing, and Diffie-Hellman key exchange protocols and elliptic curve cryptography hardware implementations
– RTL Design and implementation of MACSEC/IPSEC/AES/SHA/RSA cores for high performance networking application
– Create block-level micro-architecture specification and that outline interfaces, timing behavior, design tradeoffs, and performance goals
– Review vendor IP integration guidelines and verify the compliance throughout the design flow
– Run integrity check tools such as Lint/CDC/DFT/LEC/UPF to satisfy coding and implementation guidelines
– Participate in design verification process by reviewing test plans, coverage reports, writing assertions and other design modifications to improve verification quality
– Participate in physical implementation process by providing synthesis constraints, timing exceptions and making design updates to meet area, power and performance goals
– Be able to work and communicate with multi-site teams
– Responsible for the review of netlist releases (pre/post-route/eco, block/chip)
– ASIC product life cycle experience (requirements, design, implementation, test and post-silicon validation)
2. 芯片验证工程师-CPU
工作地： 美国
招聘人数： 1
· Responsibilities:
– Develop SOC test bench, create tests, and necessary coverage goals based on specification to verify all aspects of CPU implementation.
– Participate in defining functional specification with the architect and develop the design in Verilog with verification engineers.
– Support gate level functional verification, run regressions, manage bug tracking, analyze code & functional coverage.
– Apply advanced techniques to achieve verification and validation with the highest quality, productivity.
– Support verification, circuit, and test groups throughout design cycle and silicon bring up.
– Work with multi-disciplinary groups to ensure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design flow.
– Work independently & manage deliverables to align with the project goal.
– Develop, and maintain UVM based co-simulation environment, that include checkers, BFMs, monitors, DPI interface to reference model.
· Experience/Skills:
– Minimum of 10 years of experience in ASIC SOC designs
– Strong experience in embedded-CPU SOC design
– Strong Experience in RTL design, design verification synthesis & formality
3. Principle Engineer,PCIe Controller and PHY SOC Design
工作地： 新竹或美国
招聘人数： 1
· Responsibilities:
– RTL Design and implementation of interface logic between PCIe controller and DMA engines for high performance networking application
– Create block-level micro-architecture specification and that outline interfaces, timing behavior, design tradeoffs, and performance goals
– Review vendor IP integration guidelines and verify the compliance throughout the design flow
– Run integrity check tools such as Lint/CDC/DFT/LEC/UPF to satisfy coding and implementation guidelines
– Participate in design verification process by reviewing test plans, coverage reports, writing assertions
and other design modifications to improve verification quality
– Participate in physical implementation process by providing synthesis constraints, timing exceptions and making design updates to meet area, power and performance goals
– Be able to work and communicate with multi-site teams
– Responsible for the review of netlist releases (pre/post-route/eco, block/chip)
· Experience/Skills:
– Extensive experience in integration and validation of high speed PCIe IP core (including controller and PHY SerDes)
– Recent experience with PCIe Gen3 and Gen4 protocols
– Experience with PCIe protocol analyzers and silicon-debugging tools
– Familiarity with PCIe driver and application software for Linux/Windows
– 10+ years of ASIC RTL Design experience and Verilog/System Verilog proficiency
– Experience with multiple clock and power domains
– Familiarity with ASIC product life cycle experience (requirements, design, implementation, test and post-silicon validation)
4. Principle Engineer,DDR Controller and PHY SOC Design
工作地： 新竹或美国
招聘人数： 1
· Responsibilities:
– RTL Design and implementation of interface logic between DDR controller and DMA engines for high performance networking application
– Create block-level micro-architecture specification and that outline interfaces, timing behavior, design tradeoffs, and performance goals
– Review vendor IP integration guidelines and verify the compliance throughout the design flow
– Run integrity check tools such as Lint/CDC/DFT/LEC/UPF to satisfy coding and implementation guidelines
– Participate in design verification process by reviewing test plans, coverage reports, writing assertions
and other design modifications to improve verification quality
– Participate in physical implementation process by providing synthesis constraints, timing exceptions and making design updates to meet area, power and performance goals
– Be able to work and communicate with multi-site teams
– Responsible for the review of netlist releases (pre/post-route/eco, block/chip)
· Experience/Skills:
– Solid understanding of DDR architecture. Must have implemented/verified DDR sub systems on recent technology nodes
– Extensive experience in integration and validation of high speed DDR IP core (including controller and PHY SerDes)
– Recent experience with DDR3, DDR4 protocols
– Experience with SERDES protocol analyzers and silicon-debugging tools
– 10+ years of ASIC RTL Design experience and Verilog/System Verilog proficiency
– Experience with multiple clock and power domains
– Familiarity with ASIC product life cycle experience (requirements, design, implementation, test and post-silicon validation)
